1. Technical Field
The disclosure relates to the estimation of capacitance weight errors, more particularly to a full-digital capacitance weight error estimation method for estimating capacitance weight errors of a digital to analog converter (DAC) in a successive approximation analog to digital converter (ADC), and the successive approximation ADC using the same.
2. Related Art
The ADC is widely used in communication equipments, measurement instruments, and other various electrical devices. Generally, the ADCs may be sorted as flash ADCs, pipelined ADCs, and successive approximation ADCs, etc. Because the successive approximation ADC may have low power consumption, it is widely used in all kinds of applications.
The accuracy of the switched-capacitor type successive approximation ADC is mainly influenced by the capacitance weight errors. The smaller the capacitance weight errors are, the higher the accuracy of the successive approximation ADC is. However, in the manufacturing processes of the integrated circuits, the capacitance weight errors are unavoidable because of manufacturing process offsets. Therefore, it is the key point for the integrated circuit design to calibrate the capacitance weight errors caused by the manufacturing process offsets, so as to increase the accuracy of the successive approximation ADC.
A conventional technique to calibrate the capacitance weight error is using precision instruments for measuring the actual capacitance value, then using the focused ion beam (FIB) manner for connecting with capacitors in parallel to increase the capacitance value thereof, or using the laser trimming manner for eliminating parallel capacitors to reduce the capacitance value thereof, until the capacitance value thereof matches the expected value, which means the calibration of the capacitance value is done. For either the laser trimming manner or the FIB manner, it is necessary to use extra manpower and equipment resources for calibrating the chipped integrated circuits. This causes extra expenses and enormous time may be required, which increase the manufacturing costs.
Another conventional technique uses a resistor type DAC for generating an analog calibration voltage. After the analog calibration voltage supplies to a terminal of the calibrated capacitor, by changing the digital input code of the DAC, the voltage outputted by another terminal of the calibrated capacitor may be similar to the output voltage of the ideal capacitor without the calibration voltage. Afterward, the digital input code corresponding to the calibration voltage is stored. When the calibrated capacitor needs to be used, the digital input code is converted into the corresponding analog calibration voltage, for compensating the capacitor.
However, because the actual implemented circuits can only generate positive voltages, thus the above resistor type calibration manner is only suitable for the actual capacitance value smaller than the ideal capacitance value. That is, the above manner can only perform the one-sign calibration of the capacitance weight errors. In addition, the above manner needs an extra resistor type DAC. Thus, extra hardware is required, and the errors generated by the resistor type DAC may also influence the accuracy after the calibration.